The Different Flavors of IP Cores: Soft, Hard, and Firm

IP cores come in many forms, and each one shapes an FPGA design in a different way. Soft, hard, and firm cores all approach implementation from unique angles, which affects everything from flexibility to how tightly the design maps to hardware.

When you start exploring IP cores, you’ll encounter three main types:

Soft IP Cores

These are delivered as synthesizable HDL (Hardware Description Language) code, such as VHDL or Verilog. They are the most flexible type because you can modify the source code and adapt them to different FPGA families or specific design requirements. However, this flexibility can come at the cost of performance and may require more effort to verify.

Soft IP cores are a powerful tool for FPGA designers, offering the flexibility to create custom, application-specific systems by leveraging reusable code blocks. They represent a balance between using pre-verified functions and maintaining control over the final hardware implementation. While they demand a greater reliance on the synthesis process, their adaptability and the growing ecosystem of open-source options make them an indispensable part of the FPGA design landscape, enabling innovation and faster time-to-market for a wide range of electronic products.

Soft IP Cores in Action

New Wave Design specializes in soft IP cores for a wide range of avionics and military high-speed networking protocols. Their ARINC 818 DMA IP core solution, for example, provides a complete firmware solution for the ARINC 818 protocol, which is typically used for video and data transmission in modern avionics systems. Implementing this IP core through firmware licensing enables/engineers to quickly and effortlessly interface a new system with an ARINC 818 input or output. It converts the ARINC 818 data stream to/from an AXI4 bus, providing an efficient offload of moving video data to/from memory. The core handles all aspects of maintaining the ARINC 818 link: encoding/decoding, delimiter insertion/removal, CRC generation/checking, and transmission of idles, saving schedule and technical risk.

Hard IP Cores

These IP cores are pre-optimized and tied to a specific semiconductor manufacturing process. They are often a physical layout on the FPGA itself, offering the highest performance and reliability of the three flavors. Hard IP cores are not easily portable between different FPGA families, but they are ideal for high-speed interfaces like PCIe and multi-gigabit transceivers where performance is paramount. Hard IP blocks are significantly more power-efficient than their soft IP counterparts. The fixed logic and optimized physical layout minimize static and dynamic power consumption. Finally, Hard IP cores do not consume the reconfigurable logic resources (LUTs, flip-flops, etc.) of the FPGA fabric. This leaves more of the programmable logic available for the user’s custom firmware design.

Firm IP Cores

Firm IP cores are a middle ground. They are delivered as a gate-level net list, which provides some protection for the IP vendor while allowing for some level of placement flexibility on the FPGA. They are not as flexible as soft cores, but not as rigid as hard cores. A common real-world example of a firm IP core is some of the intellectual property generated by design tools like AMD’s (formerly Xilinx) or Altera’s (formerly Intel) core generators. For instance, a complex memory controller, a DSP filter, or a specific communication protocol may be provided as an obfuscated net list (.ngc or similar file format) that the user simply instantiates in their top-level design. This allows the user to benefit from the pre-optimized design while still having some control over its physical placement within the FPGA fabric.

IP Cores and Their Opportunities

The distinctions between soft, hard, and firm IP cores become clearer once you see how they map to real FPGA constraints and opportunities. If you’re preparing for a new build or assessing system-level needs, New Wave Design can help you navigate technical considerations and plan the right approach.